1. Field
Aspects of the present disclosure relate generally to memory devices, and more particularly, to a high-speed memory write driver circuit with voltage level shifting features.
2. Background
Power conservation for memory devices is a major objective in almost all modern electronics due to such design considerations as length of run-time as well as scalability. Many approaches have been proposed to attempt to reduce energy expenditure because memory write access may consume more than 50% of dynamic power. Further, in memory device architectures that utilize pre-charged write bitlines, wasting energy through higher leakage power is often unavoidable.
To reduce memory device power consumption, modern memory device architectures typically incorporate local write drivers to segment write bitlines hierarchically into global and local write bitlines. Global write bitlines are referred to as such because they are coupled to banks of write drivers, where each bank of write drivers includes a write driver to write to a set of bitcells using local write bitlines. In other words, in a most basic version of the modern memory device architecture, bitcells that make up memory storage are grouped into banks of memory. Each bank of memory may be programmed using a driver for driving write data to a pair of local bitlines that is coupled to each bitcell in that bank, with a decoder that is used to select which bitcell is to be programmed with the data on the local bitline. Write data is delivered to a respective write driver for the local bitlines of each bank using a single set of global bitlines.
The use of global and local bitlines allows the use of two voltage domains: a high voltage domain for the local bitlines that is needed to program the bitcells, and a low voltage domain for the global bitlines that allows data to be transferred over long distances using a lower voltage, which equates to lower power consumption. Although the described approach of using local write bitlines with associated drivers allows the two domains to be created, local write drivers increase delay because they are typically slow. For example, a 2-3 gate delay is typically incurred during a critical transition of a local bitline going low. Additional gates are also necessary to implement local write drivers, which consume precious silicon area.
Further, a level shifter must typically be used to shift the voltage level of the pair of global write bitlines to match the voltage level of the pair of local write bitlines to avoid bitcell short circuit current during write operations caused by the difference in voltage levels in the two domains. As such, all appropriate bitlines need to be setup before a write operation is activated. Thus, conventionally, when level shifters are used, the penalty incurred from the additional use of silicon area and speed reduction may be extremely high.
In order to be able to reduce power consumption while being able to maintain a dual-voltage domain memory architecture with minimal cost in space and/or operational speed, other approaches are desired.